This invention relates to semiconductor memory devices and, more particularly, to an improved flip-flop employing bipolar technology.
Flip-flops are extensively used in digital equipment. In a digital computer for example, flip-flops are commonly combined in complex irregular fashions to generate control logic signals, and are combined in simple regular fashion to form registers.
Over the past few years, the tendency of digital equipment has been to operate faster and to take less physical space. Since bipolar flip-flops are so extensively used in digital equipment, it is very desirable to make them faster and smaller.
In the past, it has been possible to fabricate many conventional flip-flops on a semiconductor chip, but they still exhibited some undesirable size and/or speed characteristics. For example, a conventional I.sup.2 L master-slave flip-flop operates quickly but requires over 30 square mils of surface area. Such flip-flops may simply be impractical to use when the particular digital equipment requires a large number of flip-flops but is restricted in size. For example, a 16-bit microprocessor chip requires that hundreds of flip-flops plus thousands of gates and thousands of ROM bits be fabricated on a square silicon chip being no larger than 300 mils on a side.
Modifications to the conventional I.sup.2 L master-slave flip-flops have been proposed which utilize less area; but some of these proposed flip-flops operate slower, and others are highly sensitive to internal feedback currents from the slave stage and thus are subject to false triggering.
Therefore, one object of the invention is to provide an improved triggerable flip-flop.
It is another objective of the invention to provide an improved flip-flop with relatively fast operating characteristics.
A further object of the invention is to provide an integrated flip-flop which requires a reduced surface area.